Open Source Real time Ethernet on Altera SoC

Benefit from highly integrated reference designs for hard real-time Ethernet solutions on Altera SoC for your PLCs, Vision System, Drives, SCADA and DCS systems. Achieve state-of-the-art performance in your master and slave field bus devices using Altera SoC along with BSD licensed openPOWERLINK technology. This provides you a single chip solution for any complex automation component.

The Altera SoC based designs are provided on the Cyclone V SoC and are supported on Quartus-II 14.0 tool-chain from Altera. The user applications in the design run on a ARM cortex A9 core and the time critical communication stack runs on a soft-core NIOS-II processor in the FPGA section of the SoC. The designs provide a network cycle time performance down to 250us with less than 40ns network jitter which make it ideal for highly time critical systems.

 

Features:

• BSD licensed
• < 250 us network cycle time
• < 40 ns jitter
• Maximum Ethernet frame size support
• 5 slaves @250 us
• > 25 slaves @1 ms
• Single chip solution
• Cross traffic
• Quartus II 14.0 support

 

Reference designs for POWERLINK on Altera SoC

 

Non OS master

• Ideal for solutions targeting highly time critical low jitter systems with network synchronization time down to 250 us and jitter < 40 ns
• Using custom openPOWERLINK hardware acceleration features on the same chip, this master design can support up to 10 slaves in 250 us of network cycle time and > 30 slaves in 1 ms of network cycle time

 

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