Skip to main content

Benefit from highly integrated reference designs for hard real-time Ethernet solutions on Zynq for your PLCs, Vision System, Drives, SCADA and DCS systems. Achieve state-of-the-art performance in your master and slave field bus devices using Zynq along with BSD licensed openPOWERLINK technology. This provides you a single chip solution for any complex automation component.

The Linux based designs provide scalable application development while then on OS designs are intended for highly time critical low jitter systems. The designs also support Ethernet POWERLINK features such as: master redundancy, upto 240 nodes in a subnet, individual request-response frames for each node and maximum Ethernet frame size for communication.



  • BSD licensed
  • < 250 us network cycle time
  • < 40 ns jitter
  • Maximum Ethernet frame size support
  • 10 slaves @250 us
  • Single chip solution
  • Cross traffic


Reference designs for POWERLINK on Zynq SoC

Linux Master


  • Caters to solutions targeting rapid time to market and low integration effort with network synchronization time as low as 500 us
  • A simple software implementation, this design runs the complete openPOWERLINK master stack on the familiar Linux environment enabling easy application development on top
  • The design supports Ethernet POWERLINK features such as redundancy, TCP/IP traffic, cross-traffic, etc


1. Software-only design – Zynq Emacps

In this design, openPOWERLINK is implemented on Linux which is running on the ARM processing system (PS) of the SoC.


2. FPGA-supported design – Zynq Hybrid
  • In this design, the ARM processing system (PS) runs the openPOWERLINK user layer along with the application.
  • The time-critical kernel part of the stack is implemented on a Microblaze softcore processor as a bare metal application which is located in the programming logic (PL) of the Zynq SoC.
  • For the network connection, the openMAC IP-Core is used. The user and kernel layer exchange the data and control information via a shared memory interface.
  • This design requires additional hardware, the AVNET expander board (AES-FMC-ISMNET-G), which is connected to the FMC connector of the Zynq ZC702 evaluation board.
  • This expander board adds two 1588 compatible 10/100 Ethernet PHYs as well as CAN, RS232 and RS485.


Non OS master


  • Ideal for solutions targeting highly time critical low jitter systems with network synchronization time down to 250 us and jitter < 40 ns
  • Using custom openPOWERLINK hardware acceleration features on the same chip, this master design can support up to 10 slaves in 250 us of network cycle time and > 30 slaves in 1 ms of network cycle time

To know more about our support for Digital Transformation and IIoT device management platform

Click here